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october 2009 doc id 15086 rev 2 1/18 18 PM8834 4 a dual low side mosfet driver features dual independent low side mosfet driver with 4 a sink and source capability independent enable for each driver driver output parallel ab ility to support higher driving capability matched propagation delays cmos/ttl compatib le input levels wide input supply voltage range: 5 v to 18 v embedded driver anti-shoot-through protection low bias switching current short propagation delays wide operative temperature range: -40 c to 105 c s08 and vfdfpn8 3x3 mm package applications switch mode power supplies dc/dc converters motor controllers line drivers class d switching amplifiers description PM8834 is a flexible, high-frequency dual low- side driver specifically designed to work with high capacitive mosfets and igbts. both PM8834 outputs can sink and source 4 a independently. higher driving current can be obtained by putting in parallel the two pwm output. PM8834 provides two enable pins which can be used to enable the operation of one or both of the output lines. PM8834 works with cmos/ttl compatible pwm signal. the driver is available in so8 (PM8834) and vfdfpn8 3x3 mm (PM8834q) packages. vfdfpn8 so8 table 1. device summary order codes temp range, cpackage packing PM8834 -40 - 105 so8 tu b e PM8834tr tape and reel PM8834q vfdfpn8 tu b e PM8834qtr tape and reel www.st.com
contents PM8834 2/18 doc id 15086 rev 2 contents 1 typical application cir cuit and block diagram . . . . . . . . . . . . . . . . . . . . 3 1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 pin description and c onnection diagram . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 device description and operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.1 input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.1.1 pwm inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.1.2 enable pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.3 parallel output operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.4 gate driver voltage flexibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.1 output series resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.2 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.3 layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
PM8834 typical application circuit and block diagram doc id 15086 rev 2 3/18 1 typical application circuit and block diagram 1.1 block diagram figure 1. block diagram !-v /54? 0- 07-? '.$ /54? 07-? 6## %.!",%? %.!",%? 3witching -anagement ,ogic $river 6## 3witching -anagement ,ogic $river 56,/ 6## 6##
pin description and connection diagram PM8834 4/18 doc id 15086 rev 2 2 pin description and connection diagram figure 2. pins connection (top view) 2.1 pin description table 2. pin description /54? 6## /54? %.!",%? 07-? '.$ 07-? %.!",%? 0- !-v 287b 9&& 287b (1$%/(b 3:0b *1' 3:0b (1$%/(b 304 pin n name function 1 enable_1 enable input for driver 1. pull low to disable driver 1 (out1 will be low, pwm1 will be ignored). even though internally pulled up to vcc with a typ. 100k resistor, it is recommended to pull high up to vcc to enable the section. the pin features ttl/ cmos compatible thresholds. 2pwm_1 pwm input signal for driver 1 featuring ttl/cmos compatible threshold and hysteresis. it is internally pulled down to gnd with a 10 a current generator. 3gnd all internal references, logic and drivers are referenced to this pin. connect to the pcb ground plane. 4pwm_2 pwm input signal for driver 2 featuring ttl/cmos compatible threshold and hysteresis. it is internally pulled down to gnd with a 10 a current generator. 5out_2 driver2 output. the output stage is ca pable of providing up to 4a drive current to the gate of a power mosfet. igbt are supported as well. a small series resistor can be useful to reduce dissipated power. 6 vcc PM8834 supply voltage. bypass with low-esr mlcc capacitor to gnd. 7out_1 driver1 output. the output stage is ca pable of providing up to 4a drive current to the gate of a power mosfet. igbt are supported as well. a small series resistor can be useful to reduce dissipated power. 8 enable_2 enable input for driver 1.pull low to disable driver1 (out1 will be low, pwm1 will be ignored). even though internally pulled up to vcc with a typ. 100k resistor, it is recommended to pull high up to vcc to enable the section. the pin features ttl/ cmos compatible thresholds.
PM8834 electrical specifications doc id 15086 rev 2 5/18 2.2 thermal data table 3. thermal data 3 electrical specifications 3.1 absolute maximum ratings table 4. absolute maximum ratings symbol parameter value unit so8 dfn8 r thja thermal resistance junction to ambient (device soldered on 2s2p pc board - 67 mm x 67 mm) 85 45 c/w r thjc thermal resistance junction to case - 5 c/w t max maximum junction temperature 150 c t stg storage temperature range -40 to 150 c t j junction temperature range -40 to 150 c t a operating ambient temperature range -40 to 105 c p tot maximum power dissipation at 25 c (device soldered on 2s2p pc board) 1.4 2.25 w symbol parameter value unit all pins to gnd -0.3 to 19 v i outx dc output current 500 ma v hbm esd capability, human body model 2kv
electrical specifications PM8834 6/18 doc id 15086 rev 2 3.2 electrical characteristics v cc = 5 v to 18 v, t j = -40 c to 105 c unless otherwise specified table 5. electrical characteristics symbol parameter test conditions min. typ. max. unit supply current and power-on i cc vcc supply current out_1, out_2 = open vcc = 10 v; t j = 25 c 3.5 ma uvlo vcc vcc turn-on vcc rising 4.4 4.6 v vcc turn-off vcc falling 3.6 3.8 v input threshold pwm_x, enable_x input high - v ih rising threshold 2.2 2.5 v input low - v il falling threshold 0.8 1.1 v drivers (out_1, out_2) r dson_h source resistance vcc = 10 v; iout = 100 ma; tj = 25 c 11.3 vcc = 10 v; iout = 100ma; full temp. range 1.5 i source source current (1) vcc = 10 v; c out to gnd = 10 nf 4a i sink sink current (1) vcc = 10 v; c out to gnd = 10 nf 5a r dson_l sink resistance vcc = 10 v; iout = 100ma;t j = 25 c 0.7 1 vcc = 10 v; iout = 100 ma; full temp. range 1.3 switching time (pwm_1,pwm_2) t r rise time vcc = 10 v; c out to gnd = 2.5 nf 10 20 ns vcc = 10 v; c out to gnd = 14 nf 45 75 ns t f fall time vcc = 10 v; c out to gnd = 2.5 nf 10 20 ns vcc = 10 v; c out to gnd = 14 nf 35 75 ns propagation delay t d_lh delay - low to high c out to gnd = 2.5 nf 15 25 35 ns t d_hl delay - high to low c out to gnd = 2.5 nf 20 30 40 ns matching between propagation delays -5 5 ns 1. parameter guaranteed by designed, not fully tested in production
PM8834 device description and operation doc id 15086 rev 2 7/18 4 device description and operation PM8834 is a dual low side driver suitable for charging and discharging large capacitive loads like mosfets or igbts used in power supplies and dc/dc modules. PM8834 can sink and source 4 a on both low side driver branch but higher driving current can be obtained by para lleling its outputs. even though this device has been designed to cope with loads requiring high peak current and fast switching time, the ultimate driving capability depends on the power dissipation in the device which must be kept below the powe r dissipation capability of the package. this aspect will be discussed in section 5.2 . for enhanced control of operation PM8834 make provision of dual independent active high enable pins (enable_1 and en able_2). connecting those pin to gnd pin, will disable the corresponding low side driver. PM8834 uses the vcc pin for supply and gnd pin for return. the dual low-side driver has been design to work with supply voltage in the range of 5 to 18 v. before vcc overcome the uvlo threshold ( uvlo vcc ), PM8834 keeps firmly-off both low- side mosfets then, after the uvlo has crossed, the pwm input keeps the control of the driver operations provided that the corresponding enable pin is active. both pwm_1 and pwm_2 are internally pulled down so if left floating the corresponding output pins are discharged. input pins (pwm_1, pwm_2, enable_1 and enable_2) are cmos/ttl compatible with capability to work also with voltages up to vcc. 4.1 input stage 4.1.1 pwm inputs the input of the PM8834 dual low side driver are compatible to cmos/ttl levels with capability to be pulled up to vcc. the relation between the input pins (pwm_1, pwm_2) and the corresponding pwm output is depicted in figure 3 . in the worst case, input levels above 2.5 v are recognized as high voltage and value below 0.8 v are recognized as low logic value. propagation delays for high-low (t d_hl ) and low-high (t d_lh ) and rise (t r ) and fall (t r ) times have been designed to ensure operation in fast switching environment. matching between delays in the two branches of the PM8834 ensure symmetry in the operations and allows parallel output functionality. each pwm input feature 10 a pull-down to default off the status of the external mosfet / igbt.
device description and operation PM8834 8/18 doc id 15086 rev 2 figure 3. timing diagram 4.1.2 enable pins PM8834 features two independent enable signals, namely enable_1 and enable_2, to control the operation of each low side driver. both enable pins are internally pulled up to vcc with a typ. 100 k resistance and are active high. in noisy application where enable_1 and enable_2 are not in use, it is strongly recommended to connect these pins to vcc directly or with a pull-up resistor. enable_1 and enable_2 are compatible to cmos/ttl levels and can be directly pulled up to vcc. by default, because of the internal pull-up, both drivers are enabled. it is possible to disable one or both low side drivers connecting the corresponding enable signal to gnd. 4.2 output stage the output stage of the PM8834 make use of st proprietary lateral dmos as depicted in figure 1. both n-dmos and p-dmos have been size d to exhibit high driving peak current as well as low on-resistance: typical peak cu rrent is 4 a while output resistances are 1 and 0.7 for p-dmos and n-dmos resistance respectively. the device features adaptive anti cross- conduction protection. PM8834 continuously monitors the status of the internal n-dmos and p-dmos: in case of a pwm transition, before switching on the desired dmos, the device waits until the other dmos is completely turned-off. no static current will then flow from vcc to gnd. t 2 t & t $?,( 07-?x /54?x t $?(, '.$ 6## 6 )( 6 ), !-v
PM8834 device description and operation doc id 15086 rev 2 9/18 4.3 parallel output operation for applications demanding high driving current capability (in excess of the 4 a provided by the single section), PM8834 allows paralleling the operation of the two drivers in order to reach higher current, up to 8 a. this configuration is depicted in figure 4 where both pwm_1 and pwm_2 and out_1 and out_2 are tied together. the matching of internal propagation delays guarantee that the two drivers are switched on and off simultaneously. figure 4. single high current (up to 8 a) low-side driver configuration 4.4 gate driver voltage flexibility PM8834 allows the user to freely-select the gate drive voltage in order to optimize the efficiency of the application. the low-side mosfet driving voltage depends on the voltage applied to vcc and can range between 5 v to 18 v. /54? 0- 07-? '.$ /54? 07-? 6## %.!",%? %.!",%? $river $river ,/!$ !-v
design guidelines PM8834 10/18 doc id 15086 rev 2 5 design guidelines 5.1 output series resistance an output resistance is generally introduced to allow high frequency operation without exceeding the maximum power dissipation of the driver package. the value of the output resistance can be obtained as described in section 5.2 . for application with supply voltages (vcc) greater than 15 v, with low capacitive loads (c g < 10 nf), caution must be taken when designing with PM8834. in these circumstances, due to its high peak curr ent capability, severe undervoltage on the output pins may occur, which, if not limited in some way, can violate the safe operating area of the output stage of the device.to avoid this phenomena it is mandatory to add a gate resistor r g of at least 1 . figure 5 is a synthetic view of the boundaries for safe operations of PM8834. figure 5. output series resistance !-v
PM8834 design guidelines doc id 15086 rev 2 11/18 5.2 power dissipation PM8834 embeds two high current low side drivers that can be used to drive high capacitive mosfets. this section estimates the power dissipated inside the device in normal applications. two main terms contribute in the device power dissipation: bias power and drivers' power. bias power (p dc ) depends on the static consumption of the device through the supply pins and it is simply obtained as follow: drivers' power is the power needed by the driver to continuously switch on and off the external mosfets; it is a function of the switching frequency and total gate charge of the selected mosfets. it can be quantified considering that the total power p sw dissipated to switch the mosfets is dissipated by three main factors: external gate resistance (when present), intrinsic mosfet resistance and intrinsi c driver resistance. this last term has to be determined to calculate the device power dissipation. the total power dissipated by each section to switch an external mosfets with gate charge q g is: when designing an application based on PM8834 it is recommended to take into consideration the effect of external gate resistors on the power dissipated by the driver. external gate resistors helps the device to dissipate the switching power since the same power p sw will be shared between the internal driv er impedance and the external resistor resulting in a general cooling of the device. referring to figure 6 , classical mosfet driver can be represented by a push-pull output stage with two different mosfets: p-dmos to drive the external gate high and n-dmos to drive the external gate low (with their own r dson : r hi, r lo ). the external power mosfet can be represented in this case as a capacitance (c g ) that stores the gate-charge (q g ) required by the external power mosfet to reach the driving voltage (v cc ). this capacitance is charged and discharged at the driver switching frequency f sw . the total power psw is dissipated among the resistive components distributed along the driving path. according to the external gate resistance and the power-mosfet intrinsic gate resistance, the driver dissipates only a portion of psw as follow (per section): the total power dissipated from the driver can then be determined as follow: p dc v cc i cc ? = p sw f sw q g v cc ? () ? = p sw 1 2 -- - c g v cc () 2 fsw r hi r hi r gate r i ++ ------------------------------------------ r lo r lo r gate r i ++ ------------------------------------------ + ?? ?? ?? ? ? = pp dc 2p ? sw + =
design guidelines PM8834 12/18 doc id 15086 rev 2 figure 6. equivalent circuit for mosfet drive 5.3 layout guidelines the first priority when placing components for these applications has to be reserved to the power section, minimizing the length of each connection and loop as much as possible. to minimize noise and voltage spikes (also emi and losses) power connections must be a part of a power plane and anyway realized by wide and thick copper traces: loop must be anyway minimized. traces between the driver and the mosfets should be short and wide to minimize the inductance of the trace so minimizing ringing in the driving signals. moreover, vias count needs to be minimized to reduce the related parasitic effect. small signal components and connections to critical nodes of the application as well as bypass capacitors for the device supply are al so important. locate the bypass capacitor (vcc capacitors) close to the device with th e shortest possible loop and use wide copper traces to minimize parasitic inductance. to improve heat dissipation, place copper area under the ic. this copper area may be connected with other layers (if available) through vias to improve the thermal conductivity. figure 7. power dissipation estimation (single channel) for capacitive load of 10 nf with no gate resistor figure 8. power dissipation estimation (single channel) for capacitive load of 10 nf with 4.7 gate resistor !-v 2 '!4% 2 ) # ' 6## ,3$2)6%2 -/3&%4 '.$ /54x 2 hi 2 lo !-v 3vz>:@ 6xsso\9rowdjh >9@ n+] n+] n+] !-v 3vz>:@ 6xsso\9rowdjh >9@ n+] n+] n+]
PM8834 design guidelines doc id 15086 rev 2 13/18 the combination of copper pad, copper plane and vias under the driver allows the device to reach its best thermal performances. figure 9. driver turn-on and turn-off paths figure 10. external components placement examplefor so8 package figure 11. external components placement example for dfn package !-v 2 '!4% 2 ) # '$ # '3 # $3 6## $2)6%2 external-/3&%4 '.$ /54x !-v /54? 6## /54? %.!",%? 07-? '.$ 07-? %.!",%? 0- !-v 304 287b 9&& 287b (1$%/(b 3:0b *1' 3:0b (1$%/(b *1' sodqh 9&& 9&&frqqhfwlrq rqlqqhuod \hu
package mechanical data PM8834 14/18 doc id 15086 rev 2 6 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack is an st trademark.
PM8834 package mechanical data doc id 15086 rev 2 15/18 table 6. vfdfpn8 mechanical data dimensions ref. mm mils min. typ. max. min. typ. max. a 0.80 0.90 1.00 31.49 35.43 39.37 a1 0.02 0.05 0.787 1.968 a2 0.65 25.59 a3 0.20 7.874 b 0.18 0.25 0.30 7.086 9.842 11.81 d 3.00 118.1 d2 2.20 2.70 86.61 106.3 e 3.00 e2 1.40 1.75 55.11 68.89 e0.50 l 0.30 0.40 0.50 11.81 15.74 19.68 package and packing information vfdfpn8 (3x3) weight: not available very thin fine pitch dual flat package no lead 0.55 0.80 2.85 3.15 2.85 3.15 ddd 0.08 3.149 21.65 31.49 112.2 124.0 118.1 112.2 124.0 19.68
package mechanical data PM8834 16/18 doc id 15086 rev 2 table 7. so-8 mechanical data dim. mm. inch min typ max min typ max a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 a2 1.10 1.65 0.043 0.065 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.010 d (1) 1. d and f does not include mold flash or protrusions. mold flash or potrusions shall not exceed 0.15mm (.006inch) per side. 4.80 5 .00 0.189 0.197 e 3.80 4.00 0.15 0.157 e 1.27 0.050 h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.40 1.27 0.016 0.050 k 0? (min.), 8? (max.) ddd 0 .10 0.004
PM8834 revision history doc id 15086 rev 2 17/18 7 revision history table 8. document revision history date revision changes 13-oct-2008 1 initial release. 21-oct-2009 2 updated figure 1 , ta b l e 2 , ta b l e 5 and section 4.1.2
PM8834 18/18 doc id 15086 rev 2 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2009 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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